FIELD OF THE INVENTION
The invention relates to an integrated semiconductor memory having a multiplicity of storage cells as well as a control device for clock-synchronous writing and reading of a data value.
Integrated semiconductor memories with clock-synchronous input and output are known as SDRAMs. Standardization is desirable for a time profile of the signals during the input and output, for example JEDEC, Solid State Technology Division, Council Ballot, JCB-98-46, 20 April 1998, Arlington, Va. According to the standardization proposal, data input and data output signals are coupled to a sampling signal (data strobe signal). The data strobe signal is produced internally to the chip. It is for its part coupled to an externally provided clock which also controls the other functional units of the semiconductor memory. The respective signal profiles for the data output and data input are presented in FIG. 5-1 and FIG. 9.1 of the JEDEC standardization proposal. The data strobe signal is also provided outside the integrated semiconductor memory. It is then available to the modules communicating with the semiconductor memory, in order to control the data interchange during a memory access. This requires a corresponding circuit outlay in the system environment of the semiconductor memory.